general description the MAX9201/max9202/max9203 high-speed, low- power, quad/dual/single comparators feature ttl logic outputs with active internal pullups. fast propagation delay (7ns typ at 5mv overdrive) makes these devices ideal for fast a/d converters and sampling circuits, line receivers, v/f converters, and many other data-discrim- ination, signal restoration applications. all comparators can be powered from separate analog and digital power supplies or from a single combined supply voltage. the analog input common-mode range includes the negative rail, allowing ground sensing when powered from a single supply. the MAX9201/ max9202/max9203 consume only 9mw per compara- tor when powered from a +5v supply. the max9202/max9203 feature output latches with ttl compatible inputs. the comparator output states are held when the latch inputs are driven low. the MAX9201 provides all the same features as the max9202/max9203 with the exception of the latches. the MAX9201/max9202/max9203 are lower power and lower cost upgrades to the max901/max902/max903 offering a 50% power savings and smaller packaging. ________________________applications ____________________________features fast 7ns propagation delay low 9mw/comparator power consumption separate analog and digital supplies flexible analog supply: +5v to +10v or 5v input voltage range includes negative supply rail ttl-compatible outputs ttl-compatible latch inputs (max9202/max9203) available in space-saving packages 8-pin sot23 (max9203) 14-pin tssop (max9202) 16-pin tssop (MAX9201) MAX9201/max9202/max9203 low-cost, 7ns, low-power voltage comparators ________________________________________________________________ maxim integrated products 1 top view 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v cc n.c. outb latchb latcha gnd ina+ ina- max9202 v dd inb+ inb- v ee n.c. outa so/tssop 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ina- ind- ind+ v cc outd outc v dd inc+ inc- MAX9201 so/tssop ina+ gnd v ee outa outb inb+ inb- in- v ee latch 1 2 8 7 v cc in+ out gnd v dd sot23 3 4 6 5 max9203 gnd latch v ee 1 2 8 7 v dd out in+ in- v cc so 3 4 6 5 max9203 pin configurations for price, delivery, and to place orders, please contact maxim distribution at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX9201 eue -40? to +85? 16 tssop MAX9201ese -40? to +85? 16 narrow so max9202 eud -40? to +85? 14 tssop max9202esd -40? to +85? 14 narrow so max9203 eka-t -40? to +85? 8 sot23-8 max9203esa -40? to +85? 8 narrow so ordering information high-speed a/d converters high-speed v/f converters line receivers high-speed signal squaring/restoration threshold detectors input trigger circuitry high-speed data sampling pwm circuits 19-1936; rev 1; 1/05
MAX9201/max9202/max9203 low cost, 7ns, low-power voltage comparators 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +5v, v ee = -5v, v dd = +5v, gnd = 0, v cm = 0, latch_ = logic high, t a = -40 c to +85 c. typical values are at t a = +25 c, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and function- al operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifica tions is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog supply voltage (v cc - v ee ) .....................................+12v digital supply voltage (v dd ) .................................................+7v differential input voltage..................(v ee - 0.3v) to (v cc + 0.3v) common mode input voltage ..........(v ee - 0.3v) to (v cc + 0.3v) latch input voltage (max9202/max9203 only) .....................-0.3v to (v dd + 0.3v) output short-circuit duration to gnd ......................................................................continuous to v dd ..................................................................................1min continuous power dissipation (t a = +70?) 8-pin sot23-8 (derate 9.1mw/? above +70?) ...727mw/? 8-pin so (derate 5.9mw/? above +70?).............471mw/? 14-pin tssop (derate 9.1mw/? above +70?) ....727mw/? 14-pin so (derate 8.3mw/? above +70?)...........667mw/? 16-pin tssop (derate 9.4mw/? above +70?) ....755mw/? 16-pin so (derate 8.7mw/? above +70?)...........696mw/? operating temperature range ...........................-45? to +85? junction temperature ......................................................+150? storage temperature range ............................-65? to +150? lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units analog supply voltage range v cc - v ee referenced to v ee 4.75 10.5 v digital supply voltage range v dd referenced to gnd 4.75 5.25 v t a = +25 c14 input offset voltage v os v cm = 0, v out = 1.4v t a = -40 c to +85 c 7.5 mv t a = +25 c 1.25 5 input bias current i b i in+ or i in- t a = -40 c to +85 c 7.0 a t a = +25 c50 250 input offset current i os v cm = 0, v out = 1.4v t a = -40 c to +85 c 450 na common-mode input voltage range v cm note 2 v ee - 0.1 v c c - 2.25 v t a = +25 c50 150 common-mode rejection ratio cmrr - 5.1v < v c m < +2.75v v ou t = 1.4v t a = -40 c to +85 c 250 v/v t a = +25 c50 150 power-supply rejection ratio psrr note 3 t a = -40 c to +85 c 250 v/v output high voltage v oh (v in+ - v in- ) > 250mv, i source = 1ma 3.0 3.5 v output low voltage v ol (v in+ - v in- ) < -250mv, i sink = 8ma 0.25 0.4 v latch input threshold voltage high v lh note 4 1.4 2 v latch input threshold voltage low v ll note 4 0.8 1.4 v latch input current high i lh v lh = 3.0v, note 4 0.5 3 a latch input current low i ll v ll = 0.3v, note 4 0.5 3 a input capacitance c in 4pf differential input impedance r ind 5m ? common-mode input impedance r incm 5.5 m ? MAX9201 4.7 7 max9202 2.5 4.0 positive analog supply current i cc note 5 max9203 1.3 2 ma
MAX9201/max9202/max9203 low cost, 7ns, low-power voltage comparators _______________________________________________________________________________________ 3 note 1: all devices are 100% production tested at t a = +25 c. all temperature limits are guaranteed by design. note 2: inferred by cmrr test. note 3: tested for +4.75v < v cc < +5.25v, and -5.25v < v ee < -4.75v with v dd = +5v, although permissible analog power-supply range is 4.75v < v cc < +10.5v for single supply operation with v ee grounded. note 4 : specification does not apply to MAX9201. note 5 : i cc tested for 4.75v < v cc < +10.5v with v ee grounded. i ee tested for -5.25v < v ee < -4.75v with v cc = +5v. i dd tested for +4.75v < v dd < +5.25v with all comparator outputs low, worst-case condition. note 6 : guaranteed by design. times are for 100mv step inputs (see propagation delay characteristics in figures 2 and 3) note 7 : maximum difference in propagation delay between two comparators in the MAX9201/max9202. parameter symbol conditions min typ max units MAX9201 3.4 5.0 max9202 1.8 3.0 negative analog supply current i ee note 5 max9203 1.0 1.6 ma MAX9201 2 3.0 max9202 1 1.5 digital supply current i dd note 5 max9203 0.5 0.8 ma MAX9201 33 44 max9202 17 24 power dissipation p d v cc = v dd = +5v, v ee = 0v max9203 9 13 mw timing characteristics (v cc = +5v, v ee = -5v, v dd = +5v, gnd = 0, v cm = 0, latch_ = logic high, t a = -40 c to +85 c. typical values are at t a = +25 c, unless otherwise noted.) (notes 1, 6) electrical characteristics (continued) (v cc = +5v, v ee = -5v, v dd = +5v, gnd = 0, v cm = 0, latch_ = logic high, t a = -40 c to +85 c. typical values are at t a = +25 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units t a = +25 c79 input-to-output high response time t pd+ v od = 5mv, c l = 15pf, i out = 2ma t a = -40 c to +85 c12 ns t a = +25 c79 input-to-output low response time t pd- v od = 5mv, c l = 15pf, i out = 2ma t a = -40 c to +85 c12 ns rise time t r c l = 15pf, i out = 2ma t a = +25 c 2.0 ns fall time t f c l = 15pf, i out = 2ma t a = +25 c 1.0 ns t a = +25 c 0.5 1.5 difference in response time between outputs ? t pd note 7 t a = -40 c to +85 c 2.5 ns latch disable to output high delay t pd +(d) note 4 10 ns latch disable to output low delay t pd -(d) note 4 10 ns minimum setup time t s note 4 2 ns minimum hold time t n note 4 1 ns minimum latch disable pulse width t pw (d) note 4 8 ns
MAX9201/max9202/max9203 low cost, 7ns, low-power voltage comparators 4 _______________________________________________________________________________________ -1.5 -0.5 -1.0 0.5 0 1.0 1.5 -40 10 -15 35 60 85 input offset voltage vs. temperature MAX9201 toc01 temperature ( c) input offset voltage (mv) 2.8 3.2 3.0 3.6 3.4 3.8 4.0 046 281012 output high voltage (v oh ) vs. load current MAX9201 toc03 load current (ma) output high voltage (v) t a = -40 c t a = +85 c t a = +25 c 0 50 100 150 200 250 300 350 400 04 2681012 output low voltage (v ol ) vs. load current MAX9201 toc04 load current (ma) output low voltage (mv) t a = +85 c t a = +25 c t a = -40 c 5.0 6.0 5.5 7.0 6.5 8.0 7.5 8.5 9.5 9.0 10.0 0 101520 5 253035 45 40 50 response time vs. input overdrive MAX9201 toc06 input overdrive (mv) response time (ns) t pd- t pd+ 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 5678910 i cc supply current (per comparator) vs. v cc supply voltage MAX9201 toc05 v cc supply voltage (v) i cc supply current (ma) t a = +85 c t a = +25 c t a = -40 c v ee = gnd typical operating characteristics (v cc = +5v, v ee = -5v, v dd = +5v, gnd = 0, v cm = 0, latch_ = logic high, v out = 1.4v, t a = +25 c, unless otherwise noted.) 0.4 0.8 0.6 1.2 1.0 1.6 1.4 1.8 -40 10 -15 35 60 85 input bias current vs. temperature MAX9201 toc02 temperature ( c) input bias current ( a) v cm = 0
MAX9201/max9202/max9203 low cost, 7ns, low-power voltage comparators _______________________________________________________________________________________ 5 typical operating characteristics (continued) (v cc = +5v, v ee = -5v, v dd = +5v, gnd = 0, v cm = 0, latch_ = logic high, v out = 1.4v, t a = +25 c, unless otherwise noted.) pin description 6.0 7.0 6.5 8.5 8.0 7.5 9.5 9.0 10.0 03040 10 20 50 60 70 80 90 response time vs. load capacitance (5mv overdrive, r load = 2.4k ? ) MAX9201 toc08 load capacitance (pf) response time (ns) t pd- t pd+ 6.5 7.0 6.8 7.5 7.3 7.8 8.0 -40-30-20-100 1020304050607080 90 response time vs. temperature (5mv overdrive) MAX9201 toc07 temperature ( c) response time (ns) t pd- t pd+ pin name function 1, 8, 9, 16 in_- negative input (channels a, b, c, d) 2, 7, 10, 15 in_+ positive input (channels a, b, c, d) 3 gnd ground 4, 5, 12, 13 out_ output (channels a, b, c, d) 6v ee negative analog supply and substrate 11 v dd positive digital supply 14 v cc positive analog supply pin name function 1, 8 in_- negative input (channels a, b) 2, 9 in_+ positive input (channels a, b) 3 gnd ground 4, 11 latch_ latch input (channels a, b) 5, 12 out_ output (channels a, b) 6, 13 n.c. no connection 7v ee negative analog supply and substrate 10 v dd positive digital supply 14 v cc positive analog supply MAX9201 max9202
applications information circuit layout because of the large gain-bandwidth transfer function of the MAX9201/max9202/max9203 special precau- tions must be taken to realize their full high-speed capability. a printed circuit board with a good, low- inductance ground plane is mandatory. all decoupling capacitors (the small 100nf ceramic type is a good choice) should be mounted as close as possible to the power-supply pins. separate decoupling capacitors for analog v cc and for digital v dd are also recommended. close attention should be paid to the bandwidth of the decoupling and terminating components. short lead lengths on the inputs and outputs are essential to avoid unwanted parasitic feedback around the comparators. solder the device directly to the printed circuit board instead of using a socket. input slew-rate requirements as with all high-speed comparators, the high gain-band- width product of the MAX9201/max9202/ max9203 can create oscillation problems when the input traverses the linear region. for clean output switching without oscilla- tion or steps in the output waveform, the input must meet minimum slew-rate requirements (0.5v/s typ). oscillation is largely a function of board layout and of coupled source impedance and stray input capacitance. both poor layout and large source impedance will cause the part to oscillate and increase the minimum slew-rate requirement. in some applications, it may be helpful to apply some positive feedback between the output and positive input. this pushes the output through the transi- tion region clearly, but applies a hysteresis in threshold seen at the input terminals. ttl output and latch inputs the comparator ttl output stages are optimized for driving low-power schottky ttl with a fan-out of four. when the latch is connected to a logic high level, the comparator is transparent and immediately responds to changes at the input terminals. when the latch is con- nected to a ttl low level, the comparator output latch- es (in the same state) the instant that the latch command is applied, and will not respond to subse- quent changes at the input. no latch is provided on the MAX9201. 6 _______________________________________________________________________________________ MAX9201/9202/9203 low cost, 7ns, low-power voltage comparators pin so sot name function 18v cc positive analog supply 2 7 in+ positive input 3 6 in- negative input 45v ee negative analog supply and substrate 54 latch latch input 6 3 gnd ground 7 2 out output 81v dd positive digital supply pin description (continued) v ee gnd v dd v cc out +10v +5v v ee gnd v dd v cc out +5v v ee gnd v dd v cc out +5v +5v -5v typical power-supply alternatives figure 1a. separate analog supply, common ground figure 1b. single +5v supply, common ground figure 1c. split ?v supply, separate ground max9203
_______________________________________________________________________________________ 7 MAX9201/9202/9203 low cost, 7ns, low-power voltage comparators power supplies the MAX9201/max9202/max9203 can be powered from separate analog and digital supplies or from a sin- gle +5v supply. the analog supply can range from +5v to +10v with v ee grounded for single-supply operation (figures 1a and 1b) or from a split 5v supply (figure 1c). the v dd digital supply always requires +5v. in high-speed, mixed-signal applications where a com- mon ground is shared, a noisy digital environment can adversely affect the analog input signal. when set up with separate supplies, the MAX9201/max9202/max9203 isolate analog and digital signals by providing a separate analog ground (v ee ) and digital ground (gnd). definition of terms v os input offset voltage: voltage applied be- tween the two input terminals to obtain ttl logic threshold (+1.4v) at the output. v in input voltage pulse amplitude: usually set to 100mv for comparator specifications. v od input voltage overdrive: usually set to 5mv and in opposite polarity to v in for comparator specifications. t pd+ input to output high delay: the propagation delay measured from the time the input signal crosses the input offset voltage to the ttl logic threshold (+1.4v) of an output low to high transition. t pd- input to output low delay: the propagation delay measured from the time the input signal crosses the input offset voltage to the ttl logic threshold (+1.4v) of an output high to low transition. t pd+ (d) latch disable to output high delay: the propagation delay measured from the latch signal crossing the ttl logic threshold (+1.4v) in a low to high transition to the point of the output crossing ttl threshold (+1.4v) in a low to high transition. tpd- (d) latch disable to output low delay: the propagation delay measured from the latch signal crossing the ttl threshold (+1.4v) in a low to high transition to the point of the output crossing ttl threshold (+1.4v) in a high to low transition. t s minimum setup time: the minimum time, before the negative transition of the latch sig- nal, that an input signal change must be pre- sent in order to be acquired and held at the outputs. t h minimum hold time: the minimum time, after the negative transition of the latch sig- nal, that an input signal must remain unchanged in order to be acquired and held at the output. t pw (d) minimum latch disable pulse width: the minimum time that the latch signal must remain high in order to acquire and hold an input signal change. figure 2. MAX9201/max9202/max9203 diagram figure 3. t pd+ response time to 5mv overdrive latch enable input t pd t pd+ (d) t pw (d) t s t h v in v od v os latch compare latch latch compare comparator output 1.4v 1.4v 5ns/div output input v od + 5mv 50mv/div 1v/div 0v 0v
MAX9201/9202/9203 low cost, 7ns, low-power voltage comparators figure 4. t pd- response time to 5mv overdrive figure 5. response-time setup 5ns/div output input v od + 5mv 50mv/div 1v/div 0v 0v precision step generator input to 10x scope probe (10m ? 14pf) v cc offset adjust 100nf 100nf 10k ? v ee = -5v 100nf output to 10x scope probe (10m ? 14pf) 1k ? 10k ? 10k ? v cc = +5v v dd = +5v r l 2.43k ? d.u.t. 100nf figure 6. response to 50mhz sine wave figure 7. response to 100mhz sine wave 5ns/div output input 2v/div 10mv/div 0v 0v 5ns/div output input 2v/div 10mv/div 0v 0v chip information MAX9201 transistor count: 348 max9202 transistor count: 176 max9203 transistor count: 116 process: bipolar maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products.
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